View LC87F2R04A_3013183.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d0909hkim 20091112-s00004 no.a1622-1/24 ver.0.61 LC87F2R04A overview the sanyo LC87F2R04A is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 4k-byte flash rom, 128-byte ram, an on- chip-debugger, sophisticated 16-bit timers/counters (may be di vided into 8-bit timers), two 8-bit timers with a prescaler, an asynchronous/synchronous sio interface, a 12-bit/8-bit 8-cha nnel ad converter, an internal reset and a 12-source 8- vector interrupt feature. features ? flash rom ? capable of on-board programming with wide range (2.2 to 5.5v) of voltage source. ? block-erasable in 128 byte units ? writable in 2-byte units ? 4096 8 bits ? ram ? 128 9 bits ? minimum bus cycle ? 83.3ns (12mhz at v dd =2.7v to 5.5v) ? 100ns (10mhz at v dd =2.2v to 5.5v) note: the bus cycle time here refers to the rom read speed. ordering number : ena1622 cmos ic 4k-byte from and 128-byte ram integrated 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F2R04A no.a1622-2/24 ? minimum instruction cycle time ? 250ns (12mhz at v dd =2.7v to 5.5v) ? 300ns (10mhz at v dd =2.2v to 5.5v) ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 11(p1n, p20, p21, p70) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? dedicated oscillator ports/input ports 2 (cf1, cf2) ? reset pin 1 ( res ) ? power pins 2 (v ss 1, v dd 1) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? sio ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? ad converter: 12 bits/8 bits 8 channels ? 12/8 bits ad converter resolution selectable ? remote control receiver circuit (sharing pins with p73, int3, and t0in) ? noise rejection function (noise filter time constant selectable from 1 tcyc/32 tcyc/128 tcyc) ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable
LC87F2R04A no.a1622-3/24 ? interrupts ? 12 sources, 8 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3 5 00023h h or l t0h 6 0002bh h or l none 7 00033h h or l none 8 0003bh h or l sio1 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 64levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? internal oscillation circuits medium-speed rc oscillation circuit: for system clock (1mhz) multifrequency rc oscillation circuit: for system clock (8mhz) ? external oscillation circuits hi-speed cf oscillation circuit: for system clock, with internal rf ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? internal reset function ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 8 levels (1.67v, 1.97v, 2.07v, 2.37v, 2.57v, 2.87v, 3.86v, and 4.35v) through option configuration. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level (7 levels: 1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v, 4.28v).
LC87F2R04A no.a1622-4/24 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer or low-voltage detection (3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc and crystal oscillato rs automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) system resetting by watchdog timer or low-voltage detection (3) having an interrupt source establis hed at either int0, int1, int2, int4 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0. ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? software break point setting for debugger. ? stepwise execution on debugger. ? real time ram data monitoring function on debugger. all the ram data map can be monitored on screen when the program is running. (the ram & sfr data can be changed by screen patch when the program is running) ? two channels of on-chip debugger pins are available to be compatible with small pin count devices. dbgp0 (p0), dbgp1 (p1) ? data security function (flash versions only) ? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security. ? package form ? mfp24s(300mil): lead-/halogen-free type ? ssop24(225mil): lead-/halogen-free type ? development tools ? on-chip debugger: tcb87 typeb+LC87F2R04A : tcb87 typec (3 wire version) +LC87F2R04A ? programming boards package programming boards mfp24s(300mil) w87f2gm ssop24(225mil) w87f2gs
LC87F2R04A no.a1622-5/24 ? flash rom programmer maker model supported version device single af9708 af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 03.11 or later lc87f2l08a af9723/af9723b(main unit) (including ando electric co., ltd. models) - - flash support group, inc. (fsg) ganged af9833(unit) (including ando electric co., ltd. models) - - af9101/af9103(main unit) (fsg) flash support group, inc. (fsg) + sanyo (note 1) onboard single/ganged sib87(interface driver) (sanyo) (note 2) - single/ganged skk/skk type b (sanyo fws) sanyo onboard single/ganged skk-dbg type b (sanyo fws) application version 1.05 or later chip data version 2.22 or later LC87F2R04A for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information. package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3112b 3287 sanyo : mfp24s(300mil) 1 12 13 24 12.5 0.63 7.6 5.4 0.15 1.0 0.35 (0.75) 1.7max 0.1 (1.5) sanyo : ssop24(225mil) 6.4 6.5 0.5 4.4 (0.5) (1.3) 24 13 1 12 0.22 0.5 0.15 0.1 1.5max
LC87F2R04A no.a1622-6/24 pin assignment sanyo: mfp24s(300mil) ?lead-/halogen-free type? sanyo: ssop24(225mil) ?lead-/halogen-free type? mfp24s ssop24 name mfp24s ssop24 name 1 p70/int0/t0lcp/an 8 13 p16/int2/t0in 2 res 14 p17/int1/t0hcp 3 v ss 1 15 p20/int4 4 cf1 16 p21/int4 5 cf2 17 p00/an0 6 v dd 1 18 p01/an1 7 p10 19 p02/an2 8 p11 20 p03/an3 9 p12 21 p04/an4 10 p13/so1/dbgp12 22 p05/an5/dbgp00 11 p14/si1/sb1/dbgp11 23 p06/an6/t6o/dbgp01 12 p15/sck1/int3/t0in/dbgp10 24 p07/t7o/dbgp02 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p70/int0/t0lcp/an8 res v ss 1 cf1 cf2 v dd 1 p10 p11 p12 p13/so1/dbgp12 p14/si1/sb1/dbgp11 p15/sck1/int3/t0in/dbgp10 p07/t7o/dbgp02 p06/an6/t6o/dbgp01 p05/an5/dbgp00 p04/an4 p03/an3 p02/an2 p01/an1 p00/an0 p21/int4 p20/int4 p17/int1/t0hcp p16/int2/t0in lc87f2r04 a top view
LC87F2R04A no.a1622-7/24 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 sio1 timer 0 port 7 adc alu flash rom pc acc b register c register psw rar ram stack pointer port 2 int4 timer 6 int0-2 int3 (noise filter) timer 7 on-chip-debugger port 2 reset control reset circuit (lvd/por) wdt res clock generator cf rc mrc
LC87F2R04A no.a1622-8/24 pin description pin name i/o description option v ss 1 - - power supply pins no v dd 1 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pin functions p06: timer 6 toggle output p07: timer 7 toggle output p00(an0) to p06(an6): ad converter input p05(dbgp00) to p07(dbgp02): on-chip debugger 0 port yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o/int3 inpu t (with noise filter)/timer 0 event input/timer 0h capture input p16: int2 input/hold reset input/time r 0 event input/timer 0l capture input p17: int1 input/hold reset i nput/timer 0h capture input p15(dbgp10) to p13(dbgp12): on-chip debugger 1 port interrupt acknowledge types rising falling rising & falling h level l level int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable yes port 2 ? 2-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p21: int4 input/hold reset input/timer 0l capture input/ timer 0h capture input interrupt acknowledge types rising falling rising & falling h level l level int4 enable enable enable disable disable p20 to p21 i/o yes port 7 ? 1-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p70(an8): ad converter input interrupt acknowledge types rising falling rising & falling h level l level int0 enable enable disable enable enable p70 i/o no res i/o external reset input/internal reset output no cf1 i ? ceramic resonator oscillator input pin ? pin function general-purpose input port no cf2 i/o ? ceramic resonator oscillator output pin ? pin function general-purpose input port no
LC87F2R04A no.a1622-9/24 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable 1 cmos programmable p20 to p21 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable note 1: the control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up conn ection is exercised in nibble (4-bit) units (p00 to 03 or p04 to 07). user option table option name option type mask version *1 flash version option selected in units of option selection cmos p00 to p07 { { 1 bit nch-open drain cmos p10 to p17 { { 1 bit nch-open drain cmos port output type p20 to p21 { { 1 bit nch-open drain 00000h program start address - *2 { - 01e00h enable: use detect function { { - disable: not used low-voltage detection reset function detect level { { - 7-level power-on reset function power-on reset level { { - 8-level * 1: mask option selection-no change possible after mask is completed. * 2: program start address of the mask version is 00000h. recommended unused pin connections recommended unused pin connections port name board software p00 to p07 open output low p10 to p17 open output low p20 to p21 open output low p70 open output low cf1 pulled low with a 100k resistor or less general-purpose input port cf2 pulled low with a 100k resistor or less general-purpose input port on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation manual" and "lc872000 series on-chip debugger pin connection requirements" notes on cf1 and cf2 pins ? when using as general-purpose input ports since the cf1 and cf2 pins are configured as cf oscillator pi ns at system reset time, it is necessary to add a current limiting resistor of 1k or greater to the cf2 pin in series when using them as general-purpose input pins.
LC87F2R04A no.a1622-10/24 differences between lc872g00 and lc872r00 series. system reset time state after system reset is released cf1/xt1 set high via the internal rf resistor cf oscillation state flash rom version lc87f2g08a cf2/xt2 set high cf oscillation state cf1/xt1 set low via the internal rf resistor cf oscillation state mask rom version lc872g08a cf2/xt2 set low cf oscillation state cf1 set low via the internal rf resistor cf oscillation state flash rom version LC87F2R04A mask rom version lc872r04a cf2 high-impedance (open) cf oscillation state power pin treatment recommendations (v dd 1, v ss 1) connect bypass capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd 1 and v ss 1 pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (l1=l1? , l2=l2?). ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should approximately 0.1 f. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2
LC87F2R04A no.a1622-11/24 absolute maximum ratings at ta = 25 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 +6.5 input voltage v i cf1, cf2 -0.3 v dd +0.3 input/output voltage v io ports 0, 1, 2 p70 -0.3 v dd +0.3 v peak output current ioph ports 0, 1, 2 cmos output select per 1 applicable pin -10 mean output current (note 1-1) iomh ports 0, 1, 2 cmos output select per 1 applicable pin -7.5 ioah(1) p10 to p14 total of all applicable pins -20 ioah(2) p15 to p17 ports 0, 2 total of all applicable pins -20 high level output current total output current ioah(3) ports 0, 1, 2 total of all applicable pins -25 iopl(1) p02 to p07 ports 1, 2 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) p70 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 mean output current (note 1-1) ioml(3) p70 per 1 applicable pin 7.5 ioal(1) p10 to p14 total of all applicable pins 50 ioal(2) ports 0, 2 p15 to p17 total of all applicable pins 60 ioal(3) ports 0, 1, 2 total of all applicable pins 70 low level output current total output current ioal(4) p70 total of all applicable pins 7.5 ma pd max(1) ta=-40 to +85 c package only 129 pd max(2) mfp24s(300mil)) ta=-40 to +85 c package with thermal resistance board (note 1-2) 229 pd max(3) ta=-40 to +85 c package only 111 power dissipation pd max(4) ssop24(225mil) ta=-40 to +85 c package with thermal resistance board (note 1-2) 334 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the mean output current is a mean value measured over 100ms. note 1-2: semi standards ther mal resistance board (size: 76.1 114.3 1.6tmm, glass epoxy) is used.
LC87F2R04A no.a1622-12/24 allowable operating conditions at ta = -40 c to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit v dd (1) 0.245 s tcyc 200 s 2.7 5.5 operating supply voltage (note 2-1) v dd (2) v dd 1 0.294 s tcyc 200 s 2.2 5.5 memory sustaining supply voltage vhd v dd 1 ram and register contents sustained in hold mode. 1.6 v ih (1) ports 1, 2 p70 port input/ interrupt side 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) port 0 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer side 2.2 to 5.5 0.9v dd v dd high level input voltage v ih (4) cf1, res 2.2 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ports 1, 2, p70 port input/ interrupt side 2.2 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) port 0 2.2 to 4.0 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.2 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (4) cf1, res 2.2 to 5.5 v ss 0.25v dd v 2.7 to 5.5 0.245 200 instruction cycle time (note 2-1) tcyc (note 2-2) 2.2 to 5.5 0.294 200 s 2.7 to 5.5 0.1 12 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=50 5% 2.2 to 5.5 0.1 10 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 ? external system clock duty=50 5% 3.0 to 5.5 0.2 24.4 mhz fmcf(1) cf1, cf2 12mhz ceramic oscillation see fig. 1. 2.7 to 5.5 12 fmcf(2) cf1, cf2 10mhz ceramic oscillation see fig. 1. 2.2 to 5.5 10 4mhz ceramic oscillation. cf oscillation normal amplifier size selected. (cflamp=0) see fig. 1 2.2 to 5.5 4 fmcf(3) cf1, cf2 4mhz ceramic oscillation. cf oscillation low amplifier size selected. (cflamp=1) see fig. 1. 2.2 to 5.5 4 fmmrc frequency variable rc oscillation. 1/2 frequency division ration. (rcctd=0) (note 2-4) 2.7 to 5.5 7.6 8.0 8.4 oscillation frequency range (note 2-3) fmrc internal medium-speed rc oscillation 2.2 to 5.5 0.5 1.0 2.0 mhz note 2-1: v dd must be held greater than or equal to 2.2v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. note 2-4: when switching the system clock, allow an oscillation stabilization time of 100 s or longer after the multifrequency rc oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
LC87F2R04A no.a1622-13/24 electrical characteristics at ta = -40 c to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2 p70 res output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.2 to 5.5 1 high level input current i ih (2) cf1 v in =v dd 2.2 to 5.5 15 i il (1) ports 0, 1, 2 p70 res output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.2 to 5.5 -1 low level input current i il (2) cf1 v in =v ss 2.2 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.35ma 2.7 to 5.5 v dd -0.4 high level output voltage v oh (3) ports 0, 1, 2 i oh =-0.15ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.4ma 2.7 to 5.5 0.4 v ol (3) ports 0, 1, 2 i ol =0.8ma 2.2 to 5.5 0.4 v ol (4) i ol =1.4ma 2.7 to 5.5 0.4 v ol (5) p70 i ol =0.8ma 2.2 to 5.5 0.4 v ol (6) i ol =25ma 4.5 to 5.5 1.5 v ol (7) i ol =4ma 2.7 to 5.5 0.4 low level output voltage v ol (8) p00, p01 i ol =2ma 2.2 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 rpu(2) ports 0, 1, 2 p70 v oh =0.9v dd when port 0 selected low-impedance pull-up. 2.2 to 4.5 18 50 230 pull-up resistance rpu(3) port 0 v oh =0.9v dd when port 0 selected high-impedance pull-up. 2.2 to 5.5 100 210 400 k vhys(1) 2.7 to 5.5 0.1v dd hysteresis voltage vhys(2) ports 1, 2 p70 res 2.2 to 5.5 0.07v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.2 to 5.5 10 pf
LC87F2R04A no.a1622-14/24 serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = 0v (note 4) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 5. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 5. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 0.05 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 5. 2.2 to 5.5 0.05 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 5. 2.2 to 5.5 (1/3)tcyc +0.08 s note 4: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40 c to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p17), int2(p16), int4(p20 to p21), ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tpih(2) tpil(2) int3(p15) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p15) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p15) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tcyc high/low level pulse width tpil(5) res ? resetting is enabled. 2.2 to 5.5 200 s
LC87F2R04A no.a1622-15/24 ad converter characteristics at ta = -40 c to +85 c, v ss 1 = 0v 12bits ad converter mode specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.4 to 5.5 12 bit 2.7 to 5.5 16 absolute accuracy et (note 6-1) 2.4 to 5.5 20 lsb 4.0 to 5.5 32 115 2.7 to 5.5 64 115 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.4 to 5.5 410 425 s analog input voltage range vain 2.4 to 5.5 v ss v dd v iainh vain=v dd 2.4 to 5.5 1 analog port input current iainl an0(p00) to an6(p06), an8(p70) vain=v ss 2.4 to 5.5 -1 a 8bits ad converter mode specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.4 to 5.5 8 bit absolute accuracy et (note 6-1) 2.4 to 5.5 1.5 lsb 4.0 to 5.5 20 90 2.7 to 5.5 40 90 conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.4 to 5.5 250 265 s analog input voltage range vain 2.4 to 5.5 v ss v dd v iainh vain=v dd 2.4 to 5.5 1 analog port input current iainl an0(p00) to an6(p06) an8(p70) vain=v ss 2.4 to 5.5 -1 a conversion time calculation formulas: 12bits ad converter mode: tcad(conversion time) = ((52/(ad division ratio)) + 2) (1/3) tcyc 8bits ad converter mode: tcad(conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc ad conversion time (tcad) external oscillation (fmcf) operating supply voltage range (v dd ) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) 12bit ad 8bit ad 4.0v to 5.5v 1/1 250ns 1/8 34.8 s 21.5 s cf-12mhz 3.0v to 5.5v 1/1 250ns 1/16 69.5 s 42.8 s 4.0v to 5.5v 1/1 300ns 1/8 41.8 s 25.8 s cf-10mhz 3.0v to 5.5v 1/1 300ns 1/16 83.4 s 51.4 s 3.0v to 5.5v 1/1 750ns 1/8 104.5 s 64.5 s cf-4mhz 2.4v to 5.5v 1/1 750ns 1/32 416.5 s 256.5 s note 6-1: the quantization error (1/2lsb ) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12 -bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
LC87F2R04A no.a1622-16/24 power-on reset (por) characteristics at ta = -40 c to +85 c, v ss 1= 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 1.67v 1.55 1.67 1.79 1.97v 1.85 1.97 2.09 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 por release voltage porrl ? select from option. (note 7-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 7. (note 7-2) 0.7 0.95 v power supply rise time poris ? power supply rise time from 0v to 1.6v. 100 ms note7-1: the por release level can be selected out of 4 levels only when the lvd reset function is disabled. note7-2: por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta = -40 c to +85 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions option selected voltage min typ max unit 1.91v 1.81 1.91 2.01 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 lvd reset voltage (note 8-2) lvdet 4.28v 4.18 4.28 4.38 v 1.91v 55 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 lvd hysteresis width lvhys ? select from option. (note 8-1) (note 8-3) ? see fig. 8. 4.28v 65 mv detection voltage unknown state lvuks ? see fig. 8. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw ? lvdet-0.5v ? see fig. 9. 0.2 ms note8-1: the lvd reset level can be selected out of 3 levels only when the lvd reset function is enabled. note8-2: lvd reset voltage specification values do not include hysteresis voltage. note8-3: lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. note8-4: lvd is in an unknown state before transistors start operation.
LC87F2R04A no.a1622-17/24 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 6.1 10 iddop(1) ? fmcf=12mhz ceramic oscillation mode ? system clock set to 12mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 3.7 6.4 2.2 to 5.5 5.3 9.1 iddop(2) ? fmcf=10mhz ceramic oscillation mode ? system clock set to 10mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.2 to 3.6 3.4 5.8 2.2 to 5.5 2.6 5.5 iddop(3) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.2 to 3.6 1.9 3.4 2.2 to 5.5 1.1 2.1 iddop(4) ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.2 to 3.6 0.56 1.1 2.2 to 5.5 0.47 1.2 iddop(5) ? external fmcf oscillation stopped. ? system clock set to internal medium speed rc oscillation. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.6 0.28 0.65 2.7 to 5.5 4.2 8.1 normal mode consumption current (note 9-1) (note 9-2) iddop(6) v dd 1 ? external fmcf oscillation stopped. ? internal medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation.(rcctd=0) ? 1/1 frequency division ratio. 2.7 to 3.6 3.3 5.6 ma note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note9-2: the consumption current values do not include operational current of lvd function if not specified. continued on next page.
LC87F2R04A no.a1622-18/24 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 2.3 4.1 iddhalt(1) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? system clock set to 12mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1.2 1.9 2.2to 5.5 1.9 3.4 iddhalt(2) ? halt mode ? fmcf=10mhz ceramic oscillation mode ? system clock set to 10mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.2 to 3.6 1.0 1.6 2.2 to 5.5 1.3 2.5 iddhalt(3) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.2 to 3.6 0.53 1.0 2.2 to 5.5 0.80 1.5 iddhalt(4) ? halt mode ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz side ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.2 to 3.6 0.31 0.62 2.2 to 5.5 0.28 0.73 iddhalt(5) ? halt mode ? external fmcf oscillation stopped. ? system clock set to internal medium speed rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.6 0.14 0.36 2.7 to 5.5 1.3 2.7 halt mode consumption current (note 9-1) (note 9-2) iddhalt(6) v dd 1 ? halt mode ? external fmcf oscillation stopped. ? internal medium speed rc oscillation stopped. ? system clock set to 8mhz with frequency variable rc oscillation. (rcctd=0) ? 1/1 frequency division ratio. 2.7 to 3.6 0.93 1.8 ma 2.2 to 5.5 0.03 25 iddhold(1) hold mode ? cf1=v dd or open (external clock mode) 2.2 to 3.6 0.02 5.9 5.0 0.03 1.2 3.3 0.02 0.56 iddhold(2) hold mode ? cf1=v dd or open (external clock mode) ? ta=-10 to +50 c 2.5 0.01 0.40 2.2 to 5.5 3.0 29 iddhold(3) hold mode ? cf1=v dd or open (external clock mode) ? lvd option selected 2.2 to 3.6 2.3 10 5.0 3.0 7.3 3.3 2.3 3.4 hold mode consumption current (note 9-1) (note 9-2) iddhold(4) v dd 1 hold mode ? cf1=v dd or open (external clock mode) ? ta=-10 to +50 c ? lvd option selected 2.5 2.0 2.9 a note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note9-2: the consumption current values do not include operational current of lvd function if not specified.
LC87F2R04A no.a1622-19/24 f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? only current of the flash block. 2.2 to 5.5 5 10 ma tfw(1) ? erasing time 20 30 ms programming time tfw(2) ? programming time 2.2 to 5.5 40 60 s characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator ? cf oscillation normal amplifier size selected (cflamp=0) ? murata circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [ms] max [ms] remarks open 680 2.2 to 5.5 0.1 0.5 12mhz smd cstce12m0g52-r0 (10) (10) open 1.0k 2.5 to 5.5 0.1 0.5 open 680 2.0 to 5.5 0.1 0.5 smd cstce10m0g52-r0 (10) (10) open 1.0k 2.1 to 5.5 0.1 0.5 open 680 2.2 to 5.5 0.1 0.5 10mhz lead cstls10m0g53-b0 (15) (15) open 1.0k 2.4 to 5.5 0.1 0.5 open 1.0k 1.9 to 5.5 0.1 0.5 smd cstce8m00g52-r0 (10) (10) open 1.5k 2.0 to 5.5 0.1 0.5 open 1.0k 2.0 to 5.5 0.1 0.5 8mhz lead cstls8m00g53-b0 (15) (15) open 1.5k 2.2 to 5.5 0.1 0.5 open 1.5k 1.9 to 5.5 0.1 0.5 smd cstcr6m00g53-r0 (15) (15) open 2.2k 2.0 to 5.5 0.1 0.5 open 1.5k 2.0 to 5.5 0.1 0.5 6mhz lead cstls6m00g53-b0 (15) (15) open 2.2k 2.1 to 5.5 0.1 0.5 open 1.5k 1.8 to 5.5 0.2 0.6 smd cstcr4m00g53-r0 (15) (15) open 3.3k 1.9 to 5.5 0.2 0.6 open 1.5k 1.8 to 5.5 0.2 0.6 4mhz lead cstls4m00g53-b0 (15) (15) open 3.3k 1.9 to 5.5 0.2 0.6 internal c1,c2
LC87F2R04A no.a1622-20/24 ? cf oscillation low amplifier size selected (cflamp=1) ? murata circuit constant oscillation stabilization time nominal frequency type oscillator name c1 [pf] c2 [pf] rf [ ] rd [ ] operating voltage range [v] typ [ms] max [ms] remarks open 1.0k 1.9 to 5.5 0.2 0.6 cstcr4m00g53-r0 (15) (15) open 2.2k 2.1 to 5.5 0.2 0.6 open 1.0k 1.8 to 5.5 0.2 0.6 smd cstcr4m00g53095-r0 (15) (15) open 2.2k 1.9 to 5.5 0.2 0.6 open 1.0k 2.0 to 5.5 0.2 0.6 cstls4m00g53-b0 (15) (15) open 2.2k 2.1 to 5.5 0.2 0.6 open 1.0k 1.8 to 5.5 0.2 0.6 4mhz lead cstls4m00g53095-b0 (15) (15) open 2.2k 1.9 to 5.5 0.2 0.6 internal c1,c2 the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 3). ? time till the oscillation gets stabilized after the cpu reset state is released. ? till the oscillation gets stabilized after the instruction fo r starting the main clock oscillation circuit is executed. ? till the oscillation gets stabilized after the hold mode is reset. (notes on the implementation of the oscillator circuit) ? oscillation is influenced by the circuit pattern layout of printed circuit board. place the oscillation-related components as close to the cpu chip and to each other as possible with the shortest possible pattern length. ? keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. ? be sure to insert a current limiting resistor (rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. ? the oscillator circuit constants shown above are sample characteristic values that ar e measured using the sanyo- designated oscillation evaluation board. since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the ic is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the ic on a user's production boar d when using the ic for applications that require high oscillation accuracy. for further information, contact your resonator vendor or sanyo semiconductor sales representative serving your locality. ? it must be noted, when replacing the flash rom version of a microcontroller with a mask rom version, that their operating voltage ranges may differ even when the oscillati on constant of the external oscillator is the same. figure 1 cf oscillator circuit figure 2 ac timing measurement point cf2 cf1 c1 rd c2 cf rf 0.5v dd
LC87F2R04A no.a1622-21/24 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time note: external oscillation circuit is selected. figure 3 oscillation stabilization times internal medium speed rc oscillation cf1, cf2 (note) state hold reset signal hold reset signal absent tmscf hold halt hold reset signal valid res cf1 operating mode reset time unpredictable reset instruction execution v dd operating v dd lower limit 0v internal medium speed rc oscillation power supply tmscf cf2
LC87F2R04A no.a1622-22/24 figure 4 reset circuit figure 5 serial i/o output waveforms figure 6 pulse input timing signal waveform c res v dd r res res note: external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information.. di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout : datain: sioclk: tsck tsckl tsckh thdi tsdi tddo t pil tpih
LC87F2R04A no.a1622-23/24 figure 7 waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only wh en power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 8 waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. por release voltage (porrl) v dd res unknown-state ( pouks ) (a) (b) reset period reset period 100 s or longer v dd res lvd hysteresis width (lvhys) unknown-state ( lvuks ) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet)
LC87F2R04A no.a1622-24/24 figure 9 low voltage detection minimum width (example of momentary power loss / voltage variation waveform) ps this catalog provides information as of november, 2009. specifications and information herein are subject to change without notice. v dd lvd reset voltage tlvdw v ss lvd release voltage lvdet-0.5v sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

▲Up To Search▲

Price & Availability of LC87F2R04A

	To Download LC87F2R04A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .